The Intel 80386 is a 32-bit processor with full backward compatibility with the 80286 and 8086. It is therefore capable of operating in three different modes: real, protected and paged-protected. In the paged-protected mode, a second level of address translation is introduced called paging. As the above diagram shows, in this mode, a logical address passes through two translation mechanisms: segmentation and paging.

Although the 80386 is a true 32-bit processor, it is capable of operating as a 16-bit processor, for example when it is emulating an 80286. Of course, it is much more powerful as a 32-bit processor because its registers are extended to 32-bits and can be used orthogonally. The 8086 and 80286 assign a specific function to many registers but the 80386 can use any 32-bit general register for addressing calculations and for the results of most arithmetic and logical operations. Performance is improved due to the use of 32-bit internal data paths and the support for larger segments, which can be as large as 4 GB. The 64 Kb maximum size of 16-bit segments generally means that segment registers have to be frequently reloaded (with new selectors) which involves a performance hit in reloading segment descriptors from memory to hidden on-chip registers. The performance gains are even higher with the 80486 (a faster highly integrated version of the 80386) where due to very efficient pipelining, most core 32-bit instructions execute in one processor clock cycle (which is one definition of a RISC processor as we will see later).

One might question the need for both segmentation and paging but they are actually designed for different purposes. Segmentation is designed to provide a very large virtual address space (64 TB max) and excellent protection. On the other hand, paging is designed to support efficient swapping between physical memory and disk and to provide some protection. However, because (a) a 32-bit segment can be as large as 4 GB, and (b) the paging mechanism provides adequate protection, Windows NT, like UNIX and OS/2 2.0, places all 32-bit code in a single 4 GB segment. This results in the so-called "flat address" model where an application simply uses 32-bit offsets (i.e. near pointers in ‘C’) to address any byte within a 4 GB linear address space (as with any other non-Intel 32-bit microprocessor!). Note that both the Intel 80386 and 80486 fix the page size at 4 Kb.

Windows NT is designed to be portable to any 32-bit (or 64-bit) processor with some form of paging mechanism. Today, Windows NT is available for the the DEC Alpha AXP processor. In contrast to a CISC (Complex Instruction Set Computer) processor, such as the Intel 80386, RISC (Reduced Instruction Set Computer) processors, such as the Alpha, aim to optimize performance by eliminating on-chip microcode (thereby leaving more chip ‘real estate’ for efficient pipelining, etc.). The goal of a RISC design is to achieve an execution rate of one instruction per clock cycle (or better!). The distinction between CISC and RISC processors is becoming blurred as silicon technology allows more and more transistors to be placed on a single chip. Intel’s 80486 already includes some RISC -type features and the Pentium includes many more.